(a) Field of the Invention
The present invention relates to a flip-chip semiconductor device having I/O modules in an internal circuit area and, more particularly, to the structure of internal test lines for testing I/O modules provided in the internal circuit area of a flip-chip semiconductor device.
(b) Description of the Related Art
Flip-chip semiconductor devices are known as ICs which are mounted on BGA packages. The flip-flop semiconductor device has peripheral input/output (I/O) pads disposed in the peripheral area of the semiconductor device, and internal I/O pads formed as flip-flop bumps and disposed in the inner area of the semiconductor device. I/O buffers of the semiconductor device are generally disposed in the peripheral area and receive/deliver external signals via the peripheral I/O pads. In general, the external signal has a higher voltage than the internal signals, and thus the I/O buffers are disposed in the peripheral area far from the internal circuit area for preventing the noise from entering the internal circuit area.
FIG. 6 shows a conventional flip-flop semiconductor device in a top plan view as viewed from the side of the I/O pads. The semiconductor device 70 includes internal circuit area 71 and a peripheral area 72 surrounding the internal circuit area 71. The internal circuit area 71 receives therein a plurality of internal I/O pads 73 formed as flip-flop bumps and arranged in a matrix. The internal I/O pads 73 arranged in a row are connected together via a power source line 80 extending in the row (y) direction and formed as the topmost layer, thereby supplying power source to the internal core blocks constituting the internal circuit. The power source lines 80 include a high-potential,(VDD) source line and a low-potential (VSS) source line or ground line, which are arranged alternately with each other.
In the peripheral area 72, there are provided test blocks 91 and 92 for testing the I/O buffers 90. The peripheral I/O pads 74 are connected to respective I/O buffers 90 to receive/deliver external signals outside the semiconductor device 70. The test blocks 91 and 92 are connected to loop test lines 81 and 82, respectively, extending along the peripheral area 72 of the semiconductor device 70, thereby testing operation of the I/O buffers 90 while using the test signals received via the peripheral I/O pads 74. It is to be noted that some of the I/O buffers 90 are omitted for depiction, and that a large number of I/O buffers 90 are generally disposed in the whole peripheral area 72 to surround the internal circuit area 71.
FIG. 7 shows the detail of some of the peripheral I/O buffers etc. disposed in the peripheral area 72. In the peripheral area 72, there are provided I/O buffers 90 and test blocks 91 and 92 arranged in a row. Each of the I/O buffers 90 and test blocks 91 and 92 is formed as a unit device having a rectangular area, wherein adjacent two unit devices are juxtaposed to each other, with the longer sides thereof being shared therebetween. Since the I/O buffer 90 and the test block 91 or 92 have the same design size, any one of the I/O buffers 90 can be replaced by a test block 91 or 92 in the peripheral area 72.
By juxtaposing the adjacent I/O buffers 90 or adjacent I/O buffer 90 and test block 91 or 92 to each other in the design, the pair of loop test line 81 and 82 are formed without an additional design. In other words, the loop test lines 81 and 82 shown in FIG. 6 are automatically arranged by disposing the unit devices without a space therebetween except for the four corner areas of the semiconductor device 70. The I/O buffer 90 has a test-operating function responding to the test signals supplied via the loop test lines 81 and 82.
Arrangement of the I/O buffers 90 in the peripheral area 72 limits the number of I/O buffers 90, which can be disposed in the semiconductor device 70, depending on the length of the peripheral area 72. Thus, if the number of external signals is larger relative to the circuit scale of the internal core blocks, the semiconductor device 70 suffers from the shortage of I/O buffers 90 which can be disposed in the semiconductor device 70. If the number of I/O buffers 90 is to be increased to avoid such a shortage, then the chip size of the semiconductor device 70 will be unreasonably increased.
For solving the above problem of the shortage of the I/O buffers, Patent Publication JP-A-2001-223335 describes a plurality of internal I/O modules each including a plurality of I/O buffers and disposed in the internal circuit area of the semiconductor device. The internal I/O module is surrounded by a guard band area for separation thereof from the internal core blocks. The described technique suppresses the adverse affect by the noise on the internal core blocks even if the external I/O signal for the I/O buffers has a higher voltage than the internal I/O signals for the internal core blocks. This obviates an undue increase in the chip size of the semiconductor device due to the increased number of I/O buffers.
However, since the internal I/O buffers disposed in the internal circuit area cannot be connected directly to the loop test lines such as 81 and 82 shown in FIG. 6, additional test lines must be disposed to connect the internal I/O buffers to the loop test lines. The additional test lines may be designed by using an auto-CAD design system as in the case of design for the signal lines of the internal core blocks. In such a case, since the internal I/O module is disposed in the internal circuit area, it may be considered that the additional test lines should be formed from an interconnect layer common with the signal lines of the internal core blocks.
FIG. 8 shows an example of arrangement of the additional test lines connected to eight I/O modules and designed by using the auto-CAD design system. This example is different from the semiconductor device 70 shown in FIG. 6 in that the semiconductor device 70A shown in FIG. 8 has internal I/O modules 90A in the internal circuit area 71A. It is to be noted that the internal I/O pads and the power source lines are omitted for depiction in FIG. 8 and that the power source lines connect the internal I/O pads together in the column (y) direction in the area where no I/O module 90A is disposed.
The test signal input from the test block 91A is delivered to the internal circuit area 71A via the loop test line 81A in the peripheral area 72A and an interconnection cell 85A disposed therein for dedicated connection of the test lines. The test signal input from the test block 92A is delivered to the internal circuit area 71A via the loop line 82A in the peripheral area 72A and an interconnection cell 86A disposed therein. The internal test lines 83A and 84A are designed for the rout thereof by using the design rule of the auto-CAD design system similarly to other internal signal lines for the internal core blocks. It is to be noted that internal interconnect lines other than the internal test lines 83A and 84A are omitted for depiction in the drawing.
FIG. 9 shows a sectional view taken along line IX—IX in FIG. 8. The topmost source lines 80A include a high-potential (VDD) source line and a VSS source line, overlying an internal core block 95A. In this example, three intermediate interconnect layers are sandwiched between the source lines 80A and the internal core block 95A in FIG. 9 and designed for routing by using the auto-CAD design system. Since the ordinary signal lines for the internal core block 95A and the internal test lines 83A and 84A are designed in a common layer, each of test lines 83A and 84A is depicted to extend adjacent to a corresponding signal line for the internal core block 61. This increases the restriction on the arrangement of the test lines and the signal lines for the internal core block 95A in consideration of the limited track area for the lines, thereby complicating the arrangement of the internal test lines 83A and 84A, as depicted in FIG. 8, while narrowing the design choice for the signal lines.
The auto-CAD design technique for the internal test lines 23 and 24 requires preparation of a netlist (interconnect list) information including connection information of the test lines from interconnection cells 85A and 86A to the I/O modules 90A. This increases the burden on the auto-CAD design system to reduce the throughput thereof. In addition, the juxtaposition of the ordinary signal lines having a potential of 1.5 volts, for example, and the internal test lines 83A and 84A having a potential of 3.3 volts, for example, causes a crosstalk therebetween, thereby affecting the test results on the I/O buffers 90A. It is generally difficult to verify the allowable range of crosstalk between the lines having different potentials, thereby complicating analysis of the test results.